// Auto-generated test bench created by VeriLogger Pro at Mon Apr 14 12:25:14 2003

// Timing model is min/max timing.

`timescale 1ns / 1ps

module syncad_top;

parameter tb_stop_time = 8700.000000;


real clk_JFall;
real clk_JRise;
real clk_MaxHL;
real clk_MaxLH;
real clk_MinHL;
real clk_MinLH;
real clk_Duty;
real clk_Period;
real clk_Offset;

task AssignExpressions;
  begin
  clk_JFall = 0.0;
  clk_JRise = 0.0;
  clk_MaxHL = 0.0;
  clk_MaxLH = 0.0;
  clk_MinHL = 0.0;
  clk_MinLH = 0.0;
  clk_Duty = 50.0;
  clk_Period = 100.0;
  clk_Offset = 0.0;
  end
endtask  // AssignExpressions

wire [1:0] tb_status;
reg [1:0] tb_status_driver;
assign tb_status = tb_status_driver;
wire rst;
reg rst_driver;
assign rst = rst_driver;
wire tx_cmd;
reg tx_cmd_driver;
assign tx_cmd = tx_cmd_driver;
wire col_det;
reg col_det_driver;
assign col_det = col_det_driver;
wire car_det;
reg car_det_driver;
assign car_det = car_det_driver;
wire clk;
wire shift_out;
wire tx_rdy;

initial
  begin
  AssignExpressions;
  tb_status_driver <= 1'b1;
  #(tb_stop_time)
  tb_status_driver <= 1'b0;
  end
initial
  begin                  //SIGNAL rst
        rst_driver <= 1'b1;
      #137.000000                    // Abs Time: 137.000000
        rst_driver <= 1'b0;
      #114.000000                    // Abs Time: 251.000000
        rst_driver <= 1'b1;
      #3164.000000                    // Abs Time: 3415.000000
        rst_driver <= 1'b0;
      #709.000000                    // Abs Time: 4124.000000
        ;
  end

initial
  begin                  //SIGNAL tx_cmd
        tx_cmd_driver <= 1'b0;
      #298.000000                    // Abs Time: 298.000000
        tx_cmd_driver <= 1'b1;
      #133.000000                    // Abs Time: 431.000000
        tx_cmd_driver <= 1'b0;
      #3206.000000                    // Abs Time: 3637.000000
        tx_cmd_driver <= 1'b1;
      #396.000000                    // Abs Time: 4033.000000
        tx_cmd_driver <= 1'b0;
      #3864.000000                    // Abs Time: 7897.000000
        ;
  end

initial
  begin                  //SIGNAL col_det
        col_det_driver <= 1'b0;
      #3625.000000                    // Abs Time: 3625.000000
        ;
  end

initial
  begin                  //SIGNAL car_det
        car_det_driver <= 1'b0;
      #3634.000000                    // Abs Time: 3634.000000
        ;
  end


wire [63:0] clk_Offset_bits = $realtobits(clk_Offset);
wire [63:0] clk_Period_bits = $realtobits(clk_Period);
wire [63:0] clk_Duty_bits = $realtobits(clk_Duty);
wire [63:0] clk_MinLH_bits = $realtobits(clk_MinLH);
wire [63:0] clk_MaxLH_bits = $realtobits(clk_MaxLH);
wire [63:0] clk_MinHL_bits = $realtobits(clk_MinHL);
wire [63:0] clk_MaxHL_bits = $realtobits(clk_MaxHL);
wire [63:0] clk_JRise_bits = $realtobits(clk_JRise);
wire [63:0] clk_JFall_bits = $realtobits(clk_JFall);

tb_clock_minmax #(1) tb_clk(tb_status[1:0],
                            clk,
                            clk_Offset_bits,
                            clk_Period_bits,
                            clk_Duty_bits,
                            clk_MinLH_bits,
                            clk_MaxLH_bits,
                            clk_MinHL_bits,
                            clk_MaxHL_bits,
                            clk_JRise_bits,
                            clk_JFall_bits);

ASM_transmitter ASM_transmitter(  .clk ( clk ),
  .rst ( rst ),
  .tx_cmd ( tx_cmd ),
  .col_det ( col_det ),
  .car_det ( car_det ),
  .shift_out ( shift_out ),
  .tx_rdy ( tx_rdy ));
  initial
    begin
    end
endmodule