module SARESTREG (clk, setB, clrB, TEST, SCAN_IN, RESET, E);
input clk, TEST, SCAN_IN, RESET;
input [3:0] setB, clrB;
output [3:0] E;
reg [3:0] E, nextE;

always @(negedge clk or posedge RESET)
  if (RESET)
    E <= 4'b0000;
  else if(TEST)
    E <= {SCAN_IN, E[3:1]};
  else
    E <= nextE;

always @(setB or clrB or E)
  nextE = (E & ~clrB) | setB;

endmodule