COMPILE;
DIRECTORY MASTER;


/****** Technology used: msu_scmos_0_8 ******/

/****** Technology used: msu_scmos ******/
MODULE sar;

INPUTS  clk,gt,start,reset,TEST,SCAN_IN;
OUTPUTS  rdy,E_3_,E_2_,E_1_,E_0_;

LEVEL FUNCTION;
DEFINE


clk = (clk);
gt = (gt);
start = (start);
reset = (reset);
TEST = (TEST);
SCAN_IN = (SCAN_IN);
rdy = (rdy);
E_3_ = (E_3_);
E_2_ = (E_2_);
E_1_ = (E_1_);
E_0_ = (E_0_);

U4(est_E51_1_=O) = nanf201(n44=A1,n45=B1);
U5(est_E51_2_=O) = nanf201(n46=A1,n47=B1);
U6(est_E51_3_=O) = nanf201(n48=A1,n49=B1);
U7(fsm_current_state79_0_=O) = norf201(reset=A1,n50=B1);
U8(fsm_current_state79_1_=O) = blf00001(reset=A1,n45=B2,n51=C2);
U9(fsm_current_state79_2_=O) = blf00001(reset=A1,n49=B2,n52=C2);
U10(n73=O) = invf101(reset=A1);
U11(n50=O) = blf00001(n53=A1,fsm_current_state_1_=B2,TEST=C2);
U12(n54=O) = norf301(n55=A1,fsm_current_state_2_=B1,fsm_current_state_1_=
  C1);
U13(n56=O) = nanf201(n42=A1,n43=B1);
U14(n57=O) = invf101(TEST=A1);
U15(n58=O) = nanf201(n59=A1,n41=B1);
U16(n60=O) = invf101(start=A1);
U17(n61=O) = invf101(gt=A1);
U18(n62=O) = invf101(E_3_=A1);
U19(n63=O) = nanf201(n64=A1,n41=B1);
U20(n65=O) = invf101(E_2_=A1);
U21(n66=O) = xorf201(fsm_current_state_1_=A1,scan=B1);
U22(n55=O) = muxf201(n61=A1,n60=B2,scan=SEL3);
U23(n67=O) = blf00101(n68=A1,n54=B2,n74=C2);
U24(est_E51_0_=O) = muxf201(E_1_=A1,n67=B2,TEST=SEL3);
U25(n53=O) = nanf201(n68=A1,n47=B1);
U26(rdy=O) = invf101(n58=A1);
U27(n45=O) = nanf401(fsm_current_state_1_=A1,scan=B1,n41=C1,n57=D1);
U28(n47=O) = nanf301(n59=A1,fsm_current_state_2_=B1,n57=C1);
U29(n68=O) = nanf301(n42=A1,n41=B1,fsm_current_state_1_=C1);
U30(n49=O) = nanf301(rdy=A1,start=B1,n57=C1);
U31(n59=O) = invf101(n56=A1);
U32(n52=O) = nanf201(TEST=A1,SCAN_IN=B1);
U33(n51=O) = blf00101(fsm_current_state_2_=A1,n59=B2,TEST=C2);
U34(n69=O) = nanf301(fsm_current_state_2_=A1,n59=B1,gt=C1);
U35(n70=O) = nanf201(E_3_=A1,n69=B1);
U36(n48=O) = muxf201(n42=A1,n70=B2,TEST=SEL3);
U37(n64=O) = muxf201(gt=A1,start=B2,fsm_current_state_1_=SEL3);
U38(n71=O) = blf00101(E_2_=A1,n63=B2,n66=C2);
U39(n46=O) = muxf201(n62=A1,n71=B2,TEST=SEL3);
U40(n72=O) = blf00101(E_1_=A1,scan=B2,n63=C2);
U41(n44=O) = muxf201(n65=A1,n72=B2,TEST=SEL3);
fsm_current_state_reg_0_(scan=Q,n42=Q_B) = dfnf311(fsm_current_state79_0_=
  DATA1,clk=CLK2);
fsm_current_state_reg_1_(fsm_current_state_1_=Q,n43=Q_B) = dfnf311(
  fsm_current_state79_1_=DATA1,clk=CLK2);
fsm_current_state_reg_2_(fsm_current_state_2_=Q,n41=Q_B) = dfnf311(
  fsm_current_state79_2_=DATA1,clk=CLK2);
est_E_reg_0_(E_0_=Q,n74=Q_B) = dfrf311(est_E51_0_=DATA1,clk=CLK2,n73=RST3
  );
est_E_reg_1_(E_1_=Q) = dfrf301(est_E51_1_=DATA1,clk=CLK2,n73=RST3);
est_E_reg_2_(E_2_=Q) = dfrf301(est_E51_2_=DATA1,clk=CLK2,n73=RST3);
est_E_reg_3_(E_3_=Q) = dfrf301(est_E51_3_=DATA1,clk=CLK2,n73=RST3);


END MODULE;

END COMPILE;
END;