module sar(clk, gt, start, reset, TEST, SCAN_IN, rdy, E);
input clk, gt, start, reset, TEST, SCAN_IN;
output [3:0] E;
output rdy;

wire [3:0] set, clr;
wire scan;

SARFSM fsm (clk, gt, start, reset, TEST, SCAN_IN, scan, set, clr, rdy);
SARESTREG est (clk, set, clr, TEST, scan, reset, E);

endmodule