Packet Transmitter

The VLSI II project involved the entire class working on three major subsections of an Ethernet style network adapter under the guidance of our professor, Dr. Nestor. Three students worked on an ASIC for the transmitter, three students worked on an ASIC for the receiver, and five students worked on a custom layout for the RAM. When all three subsections were complete, they were combined and wired together on a chip layout 8 times larger than used for the VLSI I project, and far more space-efficient.

The final chip design was complete and simulated sufficiently to be sent out to be fabricated, but we never did so because it was the last semester of senior year. Therefore we would not be able to test the physical chips even if we had them fabricated.

Chris Alworth and Andrew Lee worked with me on the transmitter. Our simulation files and synthesis files are available for perusal. Specifically, the transmitter finite state machine code may be of interest.